1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the formation of different transistor types having strained channel regions by using an embedded strain-inducing material to enhance charge carrier mobility in the channel regions.
2. Description of the Related Art
Integrated circuits have found a widespread applicability in many fields due to the continuous increase of functions that may be provided on a given chip area. Integrated circuits are composed of numerous individual circuit components, such as transistors, wherein several million or even several hundred million individual transistors may be provided in complex devices. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of reduced critical dimensions for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability.
The continuous size reduction of the critical dimensions, i.e., the gate length of the field effect transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified process steps. Furthermore, the reduction of the channel length typically requires additional design measures to counter the so-called short channel behavior of the transistors, wherein many of these measures may require the employment of sophisticated process techniques and materials, such as high-k gate dielectrics and the like, as the thickness of conventional gate dielectrics, such as silicon dioxide and the like, are pushed to the limits in view of leakage currents and the like. It has, therefore, been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to an advanced technology node while avoiding or at least postponing many of the above process adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region having a standard (100) surface orientation with the channel length direction oriented along the <110> direction may increase the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
In one approach, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked, and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Thus, complex manufacturing steps, such as etch processes, the formation of appropriate etch and growth masks and selective epitaxial growth techniques have to be incorporated into the CMOS process flow.
In other approaches, silicon/carbon material may be used for NMOS transistors to create a desired lattice mismatch specifically in the channel regions of the NMOS transistors, which may frequently be accomplished by ion implantation of carbon into the drain and source regions. However, the performance gain for transistors of different conductivity type on the basis of silicon/carbon alloys may lead to an even more complex process flow, as the various steps for the formation of respective strain layers by ion implantation may have to be appropriately integrated in the complex manufacturing flow, which may result in a less pronounced performance gain as expected.
In other conventional strategies, a silicon/carbon alloy may be formed on the basis of an epitaxial growth process, which may result in a desired high degree of tensile strain which, however, may result in an even more complex overall manufacturing flow. For example, in typical conventional process strategies, a process sequence including the encapsulation of a gate electrode structure, the etching of cavities laterally offset from a gate electrode structure and the subsequent selective epitaxial growth process is typically performed individually for P-channel transistors while masking the N-channel transistors. Similarly, the process sequence may be repeated for the N-channel transistors, while masking the P-channel transistor. Consequently, although the incorporation of an embedded strain-inducing semiconductor alloy in P-channel transistors and N-channel transistors may result in a significant increase of transistor performance for a given gate length, the high degree of complexity for implementing the process sequence described above into CMOS technology according to conventional strategies may be extremely cost intensive and may also result in an increased yield loss.
In view of the situation described above, the present disclosure relates to techniques and semiconductor devices having transistors of different conductivity type with embedded strain-inducing materials while avoiding, or at least reducing, one or more of the problems identified above.